Precision is very important in the manufacture of semiconductor integrated circuits. Semiconductor integrated circuits commonly include many transistors and active devices that are formed by implanting, depositing and etching certain substances onto the surface of a substrate. The most commonly used substrate for the manufacture of semiconductor integrated circuits is silicon, although those skilled in the art will recognize that many other known and as yet unknown substances can be used for a substrate.
The implanting, depositing and etching process steps are used in the formation of the multi-layer structure that makes up the semiconductor integrated circuit. The technique typically used to implant, deposit and etch employs a series or set of masks that expose or open windows to the surface of the semiconductor integrated circuit in formation. It is not uncommon to require dozens of different masks to implant, deposit and etch the various layers created in the multi-layer structure. Today, these structures can include, for example, three, four or even five layers of metal interconnect in addition to the active devices included in the semiconductor integrated circuit.
As the size, and accordingly the device geometries, of these semiconductor integrated circuits continues to shrink, one problem that emerges is the alignment of the many masks used in the manufacturing process. In the manufacture of sub-micron devices common today, such as 100 nanometer transistors, the alignment of the mask sets used in the manufacturing process can become critical to the operation of the resulting circuits. Improperly aligned or misaligned masks can prevent device operation and thus reduce the yield of the semiconductor integrated circuits manufactured.
One common mask alignment problem is the degree of overlay between different masks in a multiple mask set. Misalignment between successive masks used in the manufacture of the semiconductor integrated circuit can produce an overlay error that may ultimately result in the failure of the circuits to operate properly. Specifically, this overlay error may cause significant differences in the source and drain areas defined for these semiconductor integrated circuits. Overlay error between the source/drain mask, which is used to define the isolation area between the active areas, and the poly/gate mask thus becomes critical.
In order to reduce the alignment problems created by the use of multiple mask sets, certain self-alignment techniques have been attempted. What is lacking in the art is a totally self-aligned transistor and a method for making the self-aligned transistor where the gate, source, drain and isolation area of the device are all self-aligned using a single mask. What is also lacking is the provision of a mid-gap electrode in such a self-aligned transistor.